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[M68k] Fix incorrect boolean content type #152572
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@llvm/pr-subscribers-backend-m68k Author: Dan Salvato (dansalvato) ChangesM68k's SETCC instruction ( For example, this IR: define dso_local signext range(i8 0, 2) i8 @<!-- -->testBool(i32 noundef %a) local_unnamed_addr #<!-- -->0 {
entry:
%cmp = icmp eq i32 %a, 4660
%. = zext i1 %cmp to i8
ret i8 %.
} would previously build as: testBool: ; @<!-- -->testBool
cmpi.l #<!-- -->4660, (4,%sp)
seq %d0
and.l #<!-- -->255, %d0
rts Notice the testBool: ; @<!-- -->testBool
cmpi.l #<!-- -->4660, (4,%sp)
seq %d0
and.l #<!-- -->1, %d0
rts Full diff: https://github.com/llvm/llvm-project/pull/152572.diff 1 Files Affected:
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 594ea9f48c201..c6a20e211df7d 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -51,7 +51,7 @@ M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
MVT PtrVT = MVT::i32;
- setBooleanContents(ZeroOrOneBooleanContent);
+ setBooleanContents(ZeroOrNegativeOneBooleanContent);
auto *RegInfo = Subtarget.getRegisterInfo();
setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
|
Requesting review from @mshockwave |
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M68k's SETCC instruction (`scc`) distinctly fills the destination byte with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`, LLVM can mistakenly think the destination holds `0x01` instead of `0xff` and emit broken code as a result. This change corrects the boolean content type to `ZeroOrNegativeOneBooleanContent`.
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LGTM, nice catch.
M68k's SysV ABI didn't really specify the boolean values but I'm fine using SETCC's representation as that's how we lower in most cases
Updates comments for clarification.
Thank you, please feel free to merge on my behalf since I don't have write access to the repo. |
@dansalvato Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR. Please check whether problems have been caused by your change specifically, as the builds can include changes from many authors. It is not uncommon for your change to be included in a build that fails due to someone else's changes, or infrastructure issues. How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. This is a normal part of LLVM development. You can fix your changes and open a new PR to merge them again. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
M68k's SETCC instruction (`scc`) distinctly fills the destination byte with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`, LLVM can mistakenly think the destination holds `0x01` instead of `0xff` and emit broken code as a result. This change corrects the boolean content type to `ZeroOrNegativeOneBooleanContent`. For example, this IR: ```llvm define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 { entry: %cmp = icmp eq i32 %a, 4660 %. = zext i1 %cmp to i8 ret i8 %. } ``` would previously build as: ```asm testBool: ; @testBool cmpi.l llvm#4660, (4,%sp) seq %d0 and.l llvm#255, %d0 rts ``` Notice the `zext` is erroneously not clearing the low bits, and thus the register returns with 255 instead of 1. This patch fixes the issue: ```asm testBool: ; @testBool cmpi.l llvm#4660, (4,%sp) seq %d0 and.l llvm#1, %d0 rts ``` Most of the tests containing `scc` suffered from the same value error as described above, so those tests have been updated to match the new output (which also logically corrects them).
M68k's SETCC instruction (`scc`) distinctly fills the destination byte with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`, LLVM can mistakenly think the destination holds `0x01` instead of `0xff` and emit broken code as a result. This change corrects the boolean content type to `ZeroOrNegativeOneBooleanContent`. For example, this IR: ```llvm define dso_local signext range(i8 0, 2) i8 @testBool(i32 noundef %a) local_unnamed_addr #0 { entry: %cmp = icmp eq i32 %a, 4660 %. = zext i1 %cmp to i8 ret i8 %. } ``` would previously build as: ```asm testBool: ; @testBool cmpi.l llvm#4660, (4,%sp) seq %d0 and.l llvm#255, %d0 rts ``` Notice the `zext` is erroneously not clearing the low bits, and thus the register returns with 255 instead of 1. This patch fixes the issue: ```asm testBool: ; @testBool cmpi.l llvm#4660, (4,%sp) seq %d0 and.l llvm#1, %d0 rts ``` Most of the tests containing `scc` suffered from the same value error as described above, so those tests have been updated to match the new output (which also logically corrects them).
M68k's SETCC instruction (
scc
) distinctly fills the destination byte with all 1s. If boolean contents are set toZeroOrOneBooleanContent
, LLVM can mistakenly think the destination holds0x01
instead of0xff
and emit broken code as a result. This change corrects the boolean content type toZeroOrNegativeOneBooleanContent
.For example, this IR:
would previously build as:
Notice the
zext
is erroneously not clearing the low bits, and thus the register returns with 255 instead of 1. This patch fixes the issue:Most of the tests containing
scc
suffered from the same value error as described above, so those tests have been updated to match the new output (which also logically corrects them).